# Assembly Language Fundamentals (Chapter # 3)

• Chapter Outline:

• Basic Elements of Assembly Language:

• Integer Constants
• Integer Expressions
• Real Number Constants
• Character Constants
• String Constants
• Reserved Words
• Identifiers
• Directives
• Instructions
• Section Review

• Program Listing
• Program Output
• Program Description
• Program Template
• Section Review
• Assembling, Linking and Running Programs:

• Section Review
• Defining Data:

• Intrinsic Data Types
• Data Definition Statements
• Defining BYTE and SBYTE Data
• Defining WORD and SWORD Data
• Defining DWORD and SDWORD Data
• Defining QWORD Data
• Defining TBYTE Data
• Defining Real Number Data
• Little Endian Order
• Declaring Uninitialized Variables
• Section Review ( are solved in the exercises file)
• Symbolic Constants:

• Equal-Sign Directive
• Calculating the Sizes of arrays and strings
• EQU Directive
• TEXTEQU Directive
• Section Review

Basic Elements of Assembly Language (3.1)

Integer Constants (3.1.1)

• [{+ | -}] digits [radix]

• Radix: determines the integer base (default decimal), It could be the following:

• H: hexadecimal, q/o: Octal, d: decimal, b: binary, r: encoded real, t: decimal (alternative) and y: binary (alternative)
• A hexadecimal constants beginning with a letter must have a leading zero to prevent the assumption from interpreting it as identifier

Integer Expression (3.1.2)

• An integer expression is a math expression involving integer values and arithmetic operators
• The result of any integer expression is stored in 32-bits register

Real Number Constants (3.1.3)

• There are tow types of real numbers:
• Decimal: [sign] integer.[integer] [exponent]

• Exponent: E[{+ | -}] integer

Character Constants (3.1.4)

String Constants (3.1.5)

Reserved Words (3.1.6)

• Reserved of the assembly language:

• Instruction mnemonics: MOV, ADD or MUL
• Directives: which tell MASA how to assemble programs
• Attributes: BYTE, SBYTE …
• Operators
• Predefined Symbols: @data (returns constant integer values at assembly time)

Identifiers (3.1.7)

• An identifier is a programmer chosen name. it might identify a variable, constant, procedure or a code label
• Assembly Identifiers Rules:

• Length 1 à 247
• Not case sensitive
• The first character must be: letter, _, @, ? or \$
• Not as the assembler reserved words
• You can make all keywords and identifiers case-sensitive by adding –Cp command line switch when running the assembler

Directives (3.1.8)

• A directive is a command that is recognized and acted upon by the assembler as the program’s source code being assembled
• Directives are used for: defining logical segments, choosing a memory model, defining variables, creating procedure …
• .DATA Directive: identifies the area of a program variables
• .CODE Directive: identifies the area of a program that contains instructions
• PROC Directive: identifies the beginning of a procedure: name PROC

Instructions (3.1.9)

• Instruction Part:

• [Label] Mnemonic Operand(s) [Comment]
• Label: Mnemonic Operand(s) ; Comments

Label (3.1.9.1)

• A label is an identifier that acts as a place for either instructions or data
• In the processes of the scanning a source program, the assembler assigns numeric address to each program statement. A label placed just before an instruction implies the instruction’s address. Similarly, A label placed just before a variable implies the variable’s address
• Code Labels:

• Any code label must end with a colon
• Using labels as loops (as the go to spaghetti programming)
• Data Labels:

Instruction Mnemonic (3.1.9.2)

Operand (3.1.9.3)

• Operands could be zero up to three, each of which can be a register, memory operand, constant expression or I/O port
• Memory operand is specified either by the name of the variable or by a register that contains the address of a variable
• STC: set the carry flag and INC add 1 to EAX

• The following information is typically included at the top of the program listing:

• A short description of the program’s overall purpose
• The name of the programmer(s) who has written and/or revised the program
• The date of the program was written with revision date
• Comments are: ;, COMMENT user defied symbol commented code user defied symbol

Program Description (3.2.3)

• Programs are organized around segments (code, data, stack)
• The INCLUDE directive copies necessary definitions and setup information from text file named ‘the followed name’, located in to assembler’s INCLUDE directory

Assembling, Linking and Running Programs (3.3)

• The assembler produces a file containing machine language called an object file. It passed to linker, which produces an executable file

• Steps for assembling a program:

• A programmer uses a text editor to create ASCII text file named the source file
• The assembler reads the source file and produces the object file and listing file
• The linker reads the object file and copies any required procedures from the link library and combine it with the object file and produces executable file
• The OS loader utility reads the executable file into memory, branches the CPU to the program’s starting address and the program starts to execute

Defining Data (3.4)

Data Definition Statement (3.4.2)

• [name] directive initialize [,initialize]…

• ? initialize means NULL

# Basic Concepts (Chapter # 1)

• Welcome to Assembly Language (Section # 1)

• The IA-32 family began with the Intel 80386 and Pentium 4
• An assembler can optionally generate source code listing file with line numbers, memory addresses, source code statements and a cross-reference listing of symbols and variables used in a program
• Microsoft debugger called CodeView and TASM provides Turbo Debugger. For 32bit systems MSVS Debugger is preferred msdev.exe
• Types of programs that I will create:

• Environment: MS-DOS or DOS emulator
• 32-Bit Protected Mode:

• Environment: MS-Windows
• You can create programs that display text and graphics
• Assembly language has a one-to-one relationship with machine language, meaning that means one assembly language instruction corresponds to one machine language instruction
• High level languages has a one-to-many relationship with machine language, meaning that means one high level language instruction corresponds to many machine language instructions
• Assembly language fields:

• For embedded systems: air-conditioning control system, security systems
• Game programming, where some gamed require highly optimized for both space and runtime speed
• You’ll understand how computer hardware, OS and Application programs interact
• You can apply theoretical information that you took in computer architecture
• Knowing your programming language limitations
• Ability to create device drivers

• Device drivers: programs that translate general OS commands into specific references to hardware details
• Assembly language Limitations:

• The physical limitations of the processor
• The limitations of the processor native instruction set
• Two operands used in the same instruction must be the same size
• Assembly language is used to optimize certain sections of application programs for speed and to access computer hardware
• Pointer type checking in assembly is not an instruction

Virtual Machine Concept (Section # 2)

• A most efficient way to explain how a computer’s hardware and software are related is called the virtual machine concept
• Let machine language be L0. Now if we want to construct L1 language that is easier to use there are tow ways to achieve this:

• Interpretation:

• Each of L1 instructions could be decoded and then executed by a program written in L0
• Translation:

• The hole program written in L1 is converted into L0 and then executed
• The virtual machine concept:

• The Java programming language is based on the virtual machine concept that means, a program written in Java language is translated by the Java compiler into Java bit code. The later is a low-level language that quickly executed at run time by a program known as a Java virtual machine (JVM). The JVM has been implemented on many different computer systems making Java programs relatively system-independent
• The Assembly Role:

• Now let us assume that a computer’s digital logic hardware represents machine Level0 and that Level1 is implemented by an interpreter hard-wired into the processor called microarchitecture. Above this is Level2, called the instruction set architecture. This is the 1st level at which users can typically write programs, although the programs consist of binary numbers
• The Big Picture:
• The Levels Description:

• Microarchitecture (Level1):

• Computer chip manufacturer don’t generally make it possible for average users to write microinstructions. The specific microarchitecture commands are often a proprietary secret. It might require 3 or 4 microcode instructions to carry out a primitive operation such as fetching a number from memory and increment it by 1
• Instruction Set Architecture (Level2):

• Computer chip manufacturers design into the processor an instruction set that can be used to carry out basic operations such as move, add or multiply. The set of instructions is also referred to as conventional machine language or simply machine language. Each machine language instruction is executed by several microinstructions
• Operating System (Level3):

• A Level3 machine understands interactive commands by users to load and execute programs, display directories and so forth. The OS software is translated into machine code running on Level2
• OS source code might have been written in C or assembly but one compiled the OS is simply a Level2 program that can interprets Level3 commands
• Assembly Language (Level4):

• Assembly language uses short mnemonics such as ADD, SUB and MOV that are easily translated to the instruction set architecture level. Other assembly language statements such as Interrupt calls are executed directly by the OS
• High Level Languages (Level5):

• High Level-languages contain powerful statements that often translated into multiple instructions of Level4. Level5 program are translated to Level4 programs using compiler
• History of PC Assemblers:

• There is no universal assembly language specification for Intel processors. What has emerged over the years is a de facto standard, established by Microsoft’s popular MASM (Microsoft Micro Assembler) Version 5 assembler. Borland International established itself as a major competitor in the earl y 1990s with TASM (Turbo Assembler). TASM added many enhancement s. producing what was called Ideal Mode, and Borland also provided a MASM compatibility mode which matched the syntax of MASM Version 5. Microsoft released MASM 6.0 in 1992, which was a major upgrade with many new features. Since that time, Microsoft has released minor upgrades in versions 6 .11, 6. 13, 6 .14, and 6 .15, to keep up with changes to each new Pentium instruction set. The assembler syntax has not changed since version 6.0. Borland released 32-bit TASM 5.0 in 1996. which matches the MASM 6.0 syntax . There are other popular assemblers. all of which vary from MASM’s syntax to a greater or lesser degree. To name a few, there are: NASM (Netwide Assembler) for Windows and Linux, MASM 32. A shell built on top of MASM, Asm86 , and GNU assembler. distributed by the Free Software Foundation

Data Representation

• A computer stores instructions and data in memory as collections of electronic charges
• Kilobyte, Megabyte, Gigabyte, Terabyte, Petabyte, Exabyte, Zettabyte, Yottabyte
• Two’s complement representation is useful to processor designers because it removes the need for separate digital circuits to handle both addition and subtraction. For example, if presented with the expression A – B, the processor can simply convert it to an addition expression: A + (-B)
• Until a few years ago, character sets used only 8 bits. Because if the great diversity of languages around the world the 16-bit Unicode character set was created to support thousands of different character symbols
• The ASCII Code use only 7 bits from the 8 and the rest bit is used on various computers to create a proprietary character set
• A binary number is a number stored in memory in its row format, ready to be used in calculations. Binary integers are stored in multiplies of 8 bits (8, 16, 32…)
• An ASCII digit string is a string of ASCII characters, which is make to look like a number. This is simply a representation of the number and can be in any of the formats
• Converting from unsigned binary to decimal:

• Multiply by 2n
• Converting from unsigned binary to hexadecimal:

• Take every 4 digits and form one hexadecimal digit for them
• Converting from unsigned decimal to binary:

• Divide by 2n and take the remainder
• Converting from unsigned decimal to hexadecimal:

• Divide by 16n and take the remainder
• Converting from unsigned hexadecimal to decimal:

• Multiply each digit by 16n and take the sum of the all digits
• Converting from unsigned hexadecimal to binary:

• Take every digit and spread it into 4 digits
• Converting from signed binary to decimal:

• Get the two’s complement
• Convert the resulted number to decimal
• Add negative sign to the result
• Converting from signed binary to hexadecimal:

• Get the two’s complement
• Convert the resulted number to hexadecimal
• Add negative sign to the result
• Converting from signed decimal to binary:

• Convert the absolute value of the decimal integer to binary
• Form the two’s complement of the binary number from the previous step
• Converting from signed decimal to hexadecimal:

• Convert the absolute value of the decimal integer to hexadecimal
• Form the two’s complement of the hexadecimal number from the previous step
• Converting from signed hexadecimal to decimal:

• Form the two’s complement of the hexadecimal number
• Convert the number from the previous step to decimal
• Add negative sign to the resulted integer
• Converting from signed hexadecimal to binary:

• Form the two’s complement of the hexadecimal number
• Convert the number from the previous step to decimal

Boolean Operations

• The Boolean algebra was invented by George Boole, a mid nineteenth-centaury, who has never saw a computer
• Operator Precedence:

• Parentheses, NOT, AND then OR
• Multiplexer:

• It’s a digital component that uses a selector bit (S) to select one of the two outputs (X or Y). If S = False then, the function output (Z) is the same as X if true Z = Y

# IA-32 Processor Architecture (Chapter # 2)

• Chapter Outline:
• General Concepts:
• Basic Microprocessor Design
• Instruction Execution Cycle
• How Program Run
• Exercises ( are solved in the exercises file)
• IA-32 Processor Architecture:
• Modes of Operation
• Basic Execution Environment
• Floating-Point Unit
• Intel Microprocessor History
• Exercises ( are solved in the exercises file)
• IA-32 Memory Management:
• Protected Mode
• Exercises ( are solved in the exercises file)
• Components of IA-32 Microprocessor:
• Motherboard
• Video Output
• Memory
• Input-Output Ports
• Exercises ( are solved in the exercises file)
• Input-Output System:
• How it All Works
• Exercises ( are solved in the exercises file)

General Concepts (Section # 1)

Basic Microprocessor Design (2.1.1)

• Figure 2-1 shows the basic design of a hypothetical microprocessor. The central processor unit (CPU). CPU contains limited number of storage locations called register, a high-frequently clock, a control unit and an arithmetic logic unit
• The clock synchronies the internal operations of the CPU with other system components
• The control unit (CU) coordinates the sequencing of steps involved in executing machine instructions
• The arithmetic logic unit (ALU) performs arithmetic operations
• The CPU is attached to the rest of the computer via pins attached to the CPU sockets. Most of these pins connect to the data bus, control bus and address bus
• The memory storage unit is where instructions and data are held while a computer program is running
• A bus is a group of parallel wires that transfer data from one part of the computer to another
• The system bus of the computer usually consists of three different busses: data bus, control bus an address bus:
• The data bus transfers instructions and data between the CPU and memory
• The control bus uses a binary signals to synchronize the actions of all devices attached to the system bus
• The address bus holds the addresses of instructions and data when the currently executing instruction transfers between CPU and memory
• Clock:
• The most basic unit of time for machine instruction is called the machine cycle (clock cycle time), which is the time required to complete one clock pulse
• The duration of the clock cycle depends on the clock speed measured by oscillations per second. A clock that oscillates 1 billion T/S is (1 GHz). The multiply operation on the 8088 processor requires 50 clock. Instructions requiring memory access often have empty clock cycles called wait states because the differences between the speed of the CPU, the system bus and memory circuits

Instruction Execution Cycle (2.1.2)

• The execution of a single machine instruction can be divided into a sequence of individual operations called the instruction execution cycle.
• The Program Execution:
• Before it executes, a program should load into the memory
• The program counter is a register that contains the address of the next instruction
• The instruction queue is a holding area inside the microprocessor to copy instruction(s) just before they execute
• When the CPU execute a single machine instruction:
• Tree primary operations are required:
• Fetch:
• the control unit fetches the instruction, copying it from memory into the CPU and increments the program counter (PC)
• Decode:
• The CU determines the type of instruction to be executed. It passes zero or more operands to the ALU and sends signals that indicate the type of operations to be executed
• Execute:
• The ALU executes the instruction, send its data to the output operand, and updates status flags providing information about the output
• Two are required when the instruction uses a memory:
• Fetch Operands:
• The CU initiates a read operation to retrieve the operand
• Store Output Operand:
• If an output operand is in memory, the CU initiates a write operation to store the data

Multistage Pipeline (2.1.2.1)

• The processor can execute instructions in parallel by the pipelining technique
• The Intel386 used a six-stage execution cycle. Later, the Intel486 introduced piplelining
• The six-stage and the parts of the processor are the following:
• Bus Interface Unit (BIU): 2
• Accesses memory and provides input-output
• Code Prefetch Unit: 1
• Receives machine instructions from the BIU and insrets them into the instruction queue
• Instruction Decode Unit: 1
• Decodes machine instructions from the prefetch queue (instruction queue) and transfers then into microcode
• Execution Unit: 1
• Execute microcode instructions produced by the Instruction Decode Unit
• Segment Unit: 2
• Paging Unit: 3
• Translates linear addresses into physical addresses, performs page protection check and keeps a list of recently accessed pages
• In the six-stage architecture for k execution stages, n instructions requires (n * k) cycles
• In pipelining, for k execution stages, n instructions require k + (n – 1) cycles
• The preceding calculations assumes that each execution stage require 1 clock cycle to finish

Superscalar Architecture (2.1.2.2)

• A superscalar processor has two or more execution pipelines, making it possible for two instructions to be in the execution stage at the same time
• Here, for n pipelines, n instructions can be execute simultaneously
• The Intel Pentium, which had two pipelines was the 1st superscalar processor in Intel IA-32
• The Intel Pro processors was the 1st to use three pipelines
• Now instructions could complete execution in (k + n) cycles

• Accessing memory over the system bus is slower that makes the CPU waits one or more clock cycles until operands have been fetched from the memory before instructions can be executed. These wasted clocks also called wait states
• A clock cycle begins as the clock signal changes from high to low, this is called trailing edges
• What happens during a each clock cycle as memory is read:
• Cycle 1: the address bits of the memory operand are placed on the address bus (ADDR)
• Cycle 2: the Read Line (RD) is set low (0) to notify all memory that a value to be read
• Cycle 3: the CPU waits one cycle to give memory time to respond. During this cycle, the memory controller places the operand on the data bus (DATA)
• Cycle 4: the Read Line (RD) goes to 1, indicating that the CPU can read the values on the DATA
• Cache Memory:
• Cache memory holds the most recently used instructions and data
• There is two types of cache memory:
• Level 1 cache: appears inside the processor itself
• Level 2 cache: is located on separate high-speed memory chips next to CPU

How Programs Run (2.1.4)

• When the OS has a request to run a program it does the following:
• The user fires the program execution (by clicking on the .exe)
• The OS searches for the program’s filename in the current disk directory
• The OS determines the next available location in the memory and load the program there. It stores the program size and location in a descriptor table
• The OS permits the program to run its first instruction. As the program is working this called a process and it has process ID
• The OS track execution of the program and respond to its requests of system resources
• The process end itself and release any resources it was use

• Scheduler allocates a small portion of CPU time (called time slice) to each task
• A multitasking OS must run on a processor that supports task switching, which means that the processor saves the sate of each task before switching to new one
• Task state consists of the contents of the processor registers, the tasks variables and the program counter

IA-32 Processor Architecture (2.2)

Modes of Operations (2.2.1)

• IA-32 processor have three operation modes:
• Protected Mode:
• All instructions and features are available
• Each program is given a separate memory area call segments
• The processor automatically detects any attempt by a program to reference memory outside its assigned segments
• Virtual-8086 Mode:
• While in protected mode the real-address mode could be executed in a save multitasking environment
• This mode is not concerned as a separate operation mode
• It has the ability top switch to the other 2 modes
• Used with MS-DOS
• System Management Mode (SMM):
• Provides the OS with power management and system security
• This features was developed by the computer manufacturers

Basic Execution Environment (2.2.2)

• Protected mode can allocate 4GB, because the registers are 32-bit
• Real-address mode can allocate 1MB
• If the processor is in real mode and running multiple programs in virtual-8086 mode each program can access its own are of memory (1MB)

Basic Program Execution Registers

• When a processing loop is optimized for speed, registers are used inside the loop rather than variables
• The basic program execution registers (Figure 2-9) are eight general-purpose registers, six segment registers, register to hold processor status flags (EFLAGS) and an instruction pointer (EIP)

1

• General-Purpose Registers:
• Used for arithmetic and data movement
• Its either 32 or 16 bit
• Some 16 bit registers can be addressed as
two separate 8-bit values
• There are 4 registers of the eight are divided
in this way: EAX, EBX, ECX and EDX
• And there are other registers are used in real-
address mode each one of size 16 bit: SI, DI
, BP and SP
• Specialized Uses:
• EAX is used for * and /. And often called the extended accumulator register
• ECX is used as a loop counter
• ESP addresses data on the stack. It should never be used for ordinary arithmetic or data transfer. Its often called extended stack pointer register
• ESI and EDI are used by high speed memory transfer instructions. They are called extended source index register and extended destination index register
• EBP is used by high-level programming languages to reference function parameters and local variables on the stack. extended frame pointer register
• Segment Registers:
• Used as a base location for pre-assigned memory segments
• Holds: program code, variables (data) and stack segment that contain local function variables and function parameters
• Instruction Pointer (EIP):
• Contains the address of next instruction to execute
• EFLAGES registers:
• Consists of individual binary bits that either control the CPU operations or reflect CPU operation outcome
• When flag = 1 that means its assigned when 0 its clear
• Control Flags: The bits is set by the programmer to control CPU’s operations
• Status Flags:
• It reflects the outcome of an arithmetic or logical operation of the CPU
• It has many values as:
• Carry flag (CF) is set when the result of an unsigned arithmetic operations is too large to fit the destination
• Overflow flag (OF) is set when the result of a signed arithmetic operations is too large or too small to fit the destination
• Sign flag (SF) is set when the result of the CPU’s operation is negative
• Zero flag (ZF) is set when the result of the CPU’s operation is zero
• Auxiliary Carry flag (AC) is set when the result of an arithmetic operation causes a carry from bit 3 to bit 4 in an 8-bit operand
• Parity flag (PC) sums the number of bits in a number, and indicates whether the sum is even or odd

Floating Point Unit (FPU) (2.2.3)

• Previously, it was a separate chip but when Intel486 appears it was integrated into the CPU
• There are 8 floating-point data registers in the FPU ST(0) à ST(7), See 2-10
• There are tow sets of registers used for advanced multimedia programming:
• Eight 64-bit registers for use with MMX instruction set
• Eight 128-bit XMM registers used for single-instruction, multiple data(SIMD)operation

Intel Microprocessor History (2.2.4)

• Intel8086 processor:
• Created in 1978
• Has 16-bit registers
• Has 16-bit data bus
• Uses a segmented memory model
• That allows programs to allocate up to 1MP of the RAM.
• IBM used this processor (but Intenl8088) in 1980
• Intel80286 processor:
• Was 1st used in IBM-PC/AT computer
• It was the 1st Intel processor that works of protected mode
• It can address up to 16MB of RAM using 24-bit address bus

IA-32 Processor Family (2.2.4.1)

• Intel386 processor:
• Has 32-bit registers
• Has external data path
• The first member of IA-32family
• IA-32 family supports a new way of addressing virtual memory that enable the programs to allocate up to 4GB linear address space
• Intel486 processor:
• The first processor that use pipelining
• Pentium processor:
• Use superscalar design with two parallel execution pipeline
• Use 64-bit internal data bus
• The first processor in IA-32 that uses MMX technology

P6 Processor Family (2.2.4.2)

• In 1995, the P6 family of processors was introduced based on new micro-architecture design that improved execution speed and it extend the IA-32 architecture.
• Pentium Pro processor, introduced advanced techniques to improve the way of instructions was executed
• Pentium II Processor:
• Added MMX technology to P6 family
• Introduced SIMD (streaming extensions)
• With special 128-bit registers designed to move large amounts of data quickly
• Pentium 4:
• Introduced the NetBurst micro-architecture, that permits the processor to operate at much higher speeds than previous IA-32 processors
• Its oriented toward high-performance multimedia applications

CISC and RISC (2.2.4.3)

• The earliest Intel processors for the IBM-PC were based on what is called Complex Instruction Set (CISC) approach.
• The philosophy was that high-level language compilers would have less work to do if individual machine language instructions were powerful
• The disadvantage was that the instruction requires long time for the processor to decode and execute
• Reduced Instruction Set (RISC) approach consists of relatively small, short and simple number of instructions that are executed quickly. The processor directly decode and execute

IA-32 Memory Management (2.3)

• One program can work at a time
• Application programs are allowed to read and modify any are of RAM
• They can read only the ROM
• Protected Mode:
• Multiple programs can work concurrently
• Virtual-8086 Mode:
• Windows NT, 2000 and XP create a virtual machine when you run the Command

• The processor can access 1MB of memory using 20-bit addresses in the range from 0 to FFFFFh.
• The problem that Intel engineers had to solve was that the original 8086 processor had only 16-bit registers, so it was impossible to directly represent a 20-bit address. They came up with a scheme known as segmented memory. All of the memory is divided into 64KB units called segments. An analogy might be a large building, where the segments represent the floors of the building. A person can ride the elevator to a particular floor, get off and then begin following the room numbers to allocate a single room. The offset of a room can be thought as the distance from the elevator to the room

• In read-address mode, the linear address (absolute) is 20 bits, ranging from 0 to FFFFFh. But programs can’t use linear addresses directly so they express addresses using two 16-bit numbers, whish are together called segment-offset address:
• A 16-bit segment value, placed in one of the segment registers
• A 16-bit offset value
• The CPU multiplies the segment value by 10h and adds the result to the variable’s offset
• A typical program has three segments:
• code (CS): 16-bit code segment address
• Data (DS): 16-bit data segment address
• Stack (SS): 16-bit stack segment address
• ES, FS, GS can point to alternate data segments

Protected Mode (2.3.2)

• The program can allocate 4GB from 0 to FFFFFFFFh this is called flat memory model
• Its simple to use because it requires only 32-bit integer to hold the address of any instruction or variable
• The segment registers point to segment descriptor tables that the OS uses to define the locations of individual programs segments
• Here CS is for descriptor table for code segment, Ds for data segments and SS for stack

Flat Segmentation Model (2.3.2.1)

• Here all segments are mapped to the entire 32-bit physical address space of the computer
• Each segment is defined by segment descriptor a 64-bit value stored in table known as the Global Descriptor Table (GDT).
• The segment limit field can optionally indicate the amount of physical memory in the system
• The assess field contains bits that determine how the segment can be used

Multi-Segment Model (2.3.2.2)

• Here, each program is given its own table of segment descriptor called Local Descriptor Table (LDT). Each descriptor points to a segment which can be distinct from all segments used by other processes

Paging (2.3.2.3)

• This feature permits a segment to be divided into 4096 bytes blocks of memory called pages
• Paging enables the total memory used by all programs running at the same time to be much larger than the computers actual memory
• Sometimes the complete collection of pages is called virtual memory
• If a task is running, parts of it can be stored on disk if they are not currently in use. Here we say that part of the task has been paged (swapped) to disk. Other used parts (code) are loaded into memory. When the CPU wants a task from the disk it issues a page fault, causing the page containing the required code to be loaded into the memory

Components of an AI-32 Microprocessor (2.4)

• The hardware components
• Internal details of Intel processor
• Software architecture: way of organizing memory and how OS interact with hardware

Motherboard (2.4.1)

• Slots to add external main memory are called SIMM or DIMM
• BIOS (Basic Input Output System) software that is loaded to the computer chip. It use static RAM
• IDE cable connector: for internal fixed disk and CD-ROM drivers
• Programmable Interrupt Controller (PIC) handle external interrupts from hardware devices
• Programmable Interval Timer/Counter updates date and clock and controls the speaker

PCI Bus Architecture 2.4.1.1

• The PCI (Peripheral Component Interconnect) bus was developed by Intel in 1992 to provide convenient upgrade path for increasingly fast Pentium processors.

Motherboard Chipset (2.4.1.2)

• Most motherboards contain an integrated set of microprocessors and controllers called chipset

Video Output (2.4.2)

• The video adapter has tow components: video controller and video display memory
• All text and graphics appear on the computer monitor are written in the vide RAM, where the video controller then sends it to the monitor
• CRT videos use a technique called raster scanning to display images
• A digital LCD monitor receives a digital bit stream directly from the video controller and view it

Memory (2.4.3)

• Several types of memory are used:
• ROM
• EPROM (Erasable Programmable Read Only Memory):
• Can be erased slowly with alternative light and reprogrammed
• DRAM:
• The place where programs and data are kept were a program in running
• It must be refreshed within less than millisecond
• Some systems use ECC (Error Checking and Correcting)
• SRAM:
• Its used as the cache memory
• It can constantly refreshed
• VRAM:
• Stores data that appears on video display
• Located on a video controller board and optimizing for storing color pixels
• Its dual-ported
• CMOS RAM:
• Stores the system setup information
• Its refreshed by a battery

Input-Output Ports (2.4.4)

• USB Port:
• UPS 1.0 supports 12 MB/Sec data transfer
• Each USB cable has two types of connectors: upstream and downstream
• Parallel Port:
• Most printers use it
• 8 or 16 data can be transfer concurrently
• Maximum 10 feet
• Serial Port:
• It’s the slowest port
• Has the ability to send over large distance
• Mouse and modem are connected by it
• Its located on the motherboard or adopter card